1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device having a dummy region.
2. Description of the Related Art
In general, the number of internal circuits and signal lines in a semiconductor device increases with the integration degree of the semiconductor device. The internal circuits of a semiconductor device are limited to a certain amount of space. Therefore, the size of the internal circuits and the line width of the signal lines decrease as the level of integration increases. The reduction in size increases the chance that the semiconductor device may fail and serves as a factor that decreases the manufacturing yield of semiconductor devices.
For example, in a semiconductor device, such as a dynamic random access memory (DRAM), the size of a memory cell becomes smaller and the data line width becomes narrower. This results in an increase in capacity for a given area. However, there is a drawback, that is, the memory cell of the semiconductor device has an increased chance of failure as memory cell size is reduced.
A redundancy circuit is provided in the semiconductor device to compensate for the chance that a memory cell may fail. Therefore, the current yield rate of semiconductor devices is still high even given the increased probability of failure.
Generally, a semiconductor device has a redundancy circuit to compensate for a failed memory cell or a faulty line. The redundancy circuit compensates for the failure by substituting a redundancy memory cell for a failed memory cell detected during a wafer test. When the redundancy circuit receives an address corresponding to a failed memory cell, the redundancy circuit blocks the path for selection of the failed memory cell and generates a path for the selection of a redundancy memory cell. The redundancy memory cell includes a plurality of fuses for programming the addresses corresponding to the failed memory cell and also programs a plurality of fuses to compensate for the failure.
FIG. 1 is a block diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, the conventional semiconductor device 100 comprises a peripheral region 110, a first memory region 120, a first circuit region 130, a second memory region 140, and a second circuit region 150. The peripheral region 110 may be coupled to an external device (not shown). The first memory region 120 may be disposed at a side of the peripheral region 110. The first circuit region 130 may be disposed at one side of the peripheral region 110 and configured to control the first memory region 120. The second memory region 140 may be disposed on another side of the peripheral region 110. The second circuit region 150 may be disposed on a third side of the peripheral region 110 and configured to control the second memory region 140. The first and second memory regions 120 and 140 may be asymmetrically disposed about the peripheral region 110, and the first and second circuit regions 130 and 150 may be asymmetrically disposed about the peripheral region 110.
The peripheral region 110 serves as a medium between internal circuits of the first and second memory regions 120 and 140, the first and second circuit regions 130 and 150, and the external device. For example, the peripheral region 110 interfaces the internal circuits of the first and second memory regions 120 and 140, the first and second circuit regions 130 and 150, and the external device for communication of data, addresses, or commands.
The internal circuits of the first and second memory regions 120 and 140, and the first and second circuit regions 130 and 150 will now be described with reference to FIGS. 2 and 3.
FIG. 2 is a block diagram illustrating the first memory region 120 and the first circuit region 130. FIG. 3 is a block diagram illustrating the second memory region 140 and the second circuit region 150. It is noted that FIGS. 2 and 3 show an arrangement for blocking the path for selection of a failed memory cell.
Referring to FIG. 2, the first memory region 120 may include an open bit line structure including a plurality of normal memory cell regions UM00 to UM09 and DM00 to DM08 and first and second dummy memory cell regions DM09 and DM09′.
The first dummy memory cell region DM09, the ninth to first lower normal memory cell regions DM08 to DM00, the tenth to first upper normal memory cell regions UM09 to UM00, and the second dummy memory cell region DM09′ are sequentially disposed about the peripheral region 110. That is, in the column direction, the first to tenth upper normal memory cell regions UM00 to UM09 and the first to ninth lower normal memory cell regions DM00 to DM08 are serially disposed, the first dummy memory cell region DM09 is disposed under the lower normal memory cell region DM08 and the second dummy memory cell region DM09′ is disposed over the first upper normal memory cell region UM00.
The first and second dummy memory cell regions DM09 and DM09′ may serve as a normal memory cell region or a tenth lower normal memory cell region according to control of the peripheral region 110. That is, the first dummy memory cell region DM09 may serve as a half of the tenth lower normal memory cell region and the second dummy memory cell region DM09′ may serve as the other half of the tenth lower normal memory cell region. Consequently, the first memory region 120 may include the first to tenth normal memory cell regions UM00 to UM09 and the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′.
Hereinafter, the group of the first to tenth upper normal memory cell regions UM00 to UM09 is referred to as a first upper memory cell region group UMG0, and the group of the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ is referred to as a first lower memory cell region group DMG0. The term of the first to tenth upper normal memory cell regions UM00 to UM09 or the first upper memory cell region group UMG0 will be selectively used when necessary. Also, the term of the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ or the first lower memory cell region group DMG0 will be selectively used when necessary.
According to the open bit line structure, a plurality of bit line sense amplifiers may be disposed between the memory cell regions. A sense amplifier for a bit line may be disposed at a side of the memory cell region and a sense amplifier for a bit line bar may be disposed at the other side of the memory cell region. Each of the bit line sense amplifiers senses and amplifies data on a bit line and a bit line bar, each of which is coupled to different memory cell regions. According to the open bit line structure which is different from a folded bit line structure in which a bit line and a bit line bar are coupled to the same memory cell region, the first and second dummy memory cell regions DM09 and DM09′ should be disposed on both sides.
Referring back to FIG. 2, the first circuit region 130 may include first to tenth upper memory cell region selection units UBS00 to UBS09, a first upper memory cell region control unit UFS00 to USF09 and URED0, a first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ and a first lower memory cell region control unit DFS00 to DFS09 and DRED0.
The first to tenth upper memory cell region selection units UBS00 to UBS09 correspond to the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0, respectively. The first upper memory cell region control unit UFS00 to USF09 and URED0 controls the first to tenth upper memory cell region selection units UBS00 to UBS09 in response to a first row address BXAR0. The first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ correspond to the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0, respectively. The first lower memory cell region control unit DFS00 to DFS09 and DRED0 controls the first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ in response to the first row address BXAR0.
The first upper memory cell region control unit UFS00 to USF09 and URED0 may include first to tenth upper comparison units UFS00 to UFS09 and a first upper repair unit URED0.
The first to tenth upper comparison units UFS00 to UFS09 correspond to the first to tenth upper memory cell region selection units UBS00 to UBS09, respectively. The first to tenth upper comparison units UFS00 to UFS09 compare the first row address BXAR0 and each of pre-stored comparison addresses (not shown) and generate first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09. The first upper repair unit URED0 generates an upper redundancy operation signal UNXEB0 in response to the first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09.
For example, if the first row address BXAR0 and one of pre-stored comparison addresses are identical, then the first to tenth upper comparison units UFS00 to UFS09 enable a corresponding pre-signal of the first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09. The first upper repair unit URED0 disables the first to tenth upper memory cell region selection units UBS00 to UBS09 by enabling the upper redundancy operation signal UNXEB0 if one or more of the first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09 are enabled. The disabled first to tenth upper memory cell region selection units UBS00 to UBS09 do not select the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0 regardless of any signal (not shown) for selecting the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0.
The first lower memory cell region control unit DFS00 to DFS09 and DRED0 may include first to tenth lower comparison units DFS00 to DFS09 and a first lower repair unit DRED0.
The first to tenth lower comparison units DFS00 to DFS09 correspond to the first to tenth lower memory cell region selection units DBS00 to DBS09, respectively. The first to tenth lower comparison units DFS00 to DFS09 compare the first row address BXAR0 and each of pre-stored comparison addresses (not shown) and generate first to tenth lower redundancy pre-signals DXHITB00 to DXHITB09. The first lower repair unit DRED0 generates a lower redundancy operation signal DNXEB0 in response to the first to tenth lower redundancy pre-signals DXHITB00 to DXHITB09.
For example, if the first row address BXAR0 and one of pre-stored comparison addresses are identical, then the first to tenth lower comparison units DFS00 to DFS09 enable corresponding first to tenth lower redundancy pre-signals DXHITB00 to DXHITB09. The first lower repair unit DRED0 disables the first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ by enabling the lower redundancy operation signal DNXEB0 if one or more of the first to tenth lower redundancy pre-signals DXHITB00 to DXHITB09 are enabled. The disabled first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ do not select the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0 regardless of any signal (not shown) for selecting the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0.
Referring to FIG. 3, the second memory region 140 may include a plurality of normal memory cell regions UM10 to UM19 and DM10 to DM18 and first and second dummy memory cell regions DM19 and DM19′ according to the open bit line structure.
The second dummy memory cell region DM19′, the first to tenth upper normal memory cell regions UM10 to UM19, the first to ninth lower normal memory cell regions DM10 to DM18, and the first dummy memory cell region DM09 may be sequentially disposed about the peripheral region 110. That is, in the column direction, the first to tenth upper normal memory cell regions UM10 to UM19 and the first to ninth lower normal memory cell regions DM10 to DM18 are serially disposed, the first dummy memory cell region DM19 is disposed under the lower normal memory cell region DM18 and the second dummy memory cell region DM19′ is dispose over the first upper normal memory cell region UM10.
The first and second dummy memory cell regions DM19 and DM19′ may serve as a normal memory cell region or a tenth lower normal memory cell region according to control of the peripheral region 110. That is, the first dummy memory cell region DM19 may serve as a half of the tenth lower normal memory cell region and the second dummy memory cell region DM19′ may serve as the other half of the tenth lower normal memory cell region. Consequently, the second memory region 140 may include the first to tenth normal memory cell regions UM10 to UM19 and the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′.
The group of the first to tenth upper normal memory cell regions UM10 to UM19 is referred to as a second upper memory cell region group UMG1, and the group of the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ is referred to as a second lower memory cell region group DMG1. The term of the first to tenth upper normal memory cell regions UM10 to UM19 or the second upper memory cell region group UMG1 will be selectively used when necessary. Also, appropriate indication between the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ and the second lower memory cell region group DMG1 will be used when necessary.
The second circuit region 150 may include first to tenth upper memory cell region selection units UBS10 to UBS19, a second upper memory cell region control unit UFS10 to USF 19 and URED1, a first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ and a second lower memory cell region control unit DFS10 to DFS19 and DRED1.
The first to tenth upper memory cell region selection units UBS10 to UBS19 correspond to the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1, respectively. The second upper memory cell region control unit UFS10 to USF19 and URED1 controls the first to tenth upper memory cell region selection units UBS10 to UBS19 in response to a second row address BXAR1. The first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ correspond to the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1, respectively. The second lower memory cell region control unit DFS10 to DFS19 and DRED1 controls the first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ in response to the second row address BXAR1.
The second upper memory cell region control unit UFS10 to USF19 and URED1 may include first to tenth upper comparison units UFS10 to UFS19 and a second upper repair unit URED1.
The first to tenth upper comparison units UFS10 to UFS19 correspond to the first to tenth upper memory cell region selection units UBS10 to UBS19, respectively. The first to tenth upper comparison units UFS10 to UFS19 compare the second row address BXAR1 and each of pre-stored comparison addresses (not shown) and generate first to tenth upper redundancy pre-signals UXHITB10 to UXHITB19. The second upper repair unit URED1 generates an upper redundancy operation signal UNXEB1 in response to the first to tenth upper redundancy pre-signals UXHITB10 to UXHITB19.
For example, if the second row address BXAR1 and one of pre-stored comparison addresses are identical, then the first to tenth upper comparison units UFS10 to UFS19 enable corresponding first to tenth upper redundancy pre-signals UXHITB10 to UXHITB19. The second upper repair unit URED1 disables the first to tenth upper memory cell region selection units UBS10 to UBS19 by enabling the upper redundancy operation signal UNXEB1 if one or more of the first to tenth upper redundancy pre-signals UXHITB10 to UXHITB19 are enabled. The disabled first to tenth upper memory cell region selection units UBS10 to UBS19 do not select the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1 regardless of any signal (not shown) for selecting the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1.
The second lower memory cell region control unit DFS10 to DFS19 and DRED1 includes first to tenth lower comparison units DFS10 to DFS19 and a second lower repair unit DRED1.
The first to tenth lower comparison units DFS10 to DFS19 correspond to the first to tenth lower memory cell region selection units DBS10 to DBS19, respectively. The first to tenth lower comparison units DFS10 to DFS19 compare the second row address BXAR1 and each of pre-stored comparison addresses (not shown) and generate first to tenth lower redundancy pre-signals DXHITB10 to DXHITB19. The second lower repair unit DRED1 generates a lower redundancy operation signal DNXEB1 in response to the first to tenth lower redundancy pre-signals DXHITB10 to DXHITB19.
For example, if the second row address BXAR1 and one of pre-stored comparison addresses are identical, then the first to tenth lower comparison units DFS10 to DFS19 enable corresponding first to tenth lower redundancy pre-signals DXHITB10 to DXHITB19. The second lower repair unit DRED1 disables the first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ by enabling the lower redundancy operation signal DNXEB1 if one or more of the first to tenth lower redundancy pre-signals DXHITB10 to DXHITB19 are enabled. The disabled first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ do not select the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1 regardless of any signal (not shown) for selecting the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1.
The operation of a conventional semiconductor device 100 will now be described.
Operation of the first circuit region 130 is as follows.
If the first row address BXAR0 is input with a write command or a read command, then the first upper memory cell region control unit UFS00 to USF09 and URED0 and the first lower memory cell region control unit DFS00 to DSF09 and DRED0 determine whether or not to enable the upper redundancy operation signal UNXEB0 based on whether or not the first row address BXAR0 corresponds to a failed memory cell.
For example, the first to tenth upper comparison units UFS00 to UFS09 compare the first row address BXAR0 to each of the pre-stored comparison addresses and generate the first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09. The first upper repair unit URED0 enables the upper redundancy operation signal UNXEB0 if one or more of the first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09 are enabled. The first to tenth lower comparison units DFS00 to DFS09 compare the first row address BXAR0 and each of the pre-stored comparison addresses and generate the first to tenth lower redundancy pre-signals DXHITB00 to DXHITB09. The first lower repair unit DRED0 enables the lower redundancy operation signal DNXEB0 if one or more of the first to tenth lower redundancy pre-signals DXHITB00 to DXHITB09 are enabled.
Enablement of the first to tenth upper memory cell region selection units UBS00 to UBS09 depends on the upper redundancy operation signal UNXEB0.
For example, the first to tenth upper memory cell region selection units UBS00 to UBS09 do not select the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0, regardless of any signal for selecting the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0, if the upper redundancy operation signal UNXEB0 is enabled. This is to prevent selection of a failed memory cell. On the other hand, the first to tenth upper memory cell region selection units UBS00 to UBS09 select one or more of the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0 according to a signal for selecting the first to tenth upper normal memory cell regions UM00 to UM09 of the first upper memory cell region group UMG0 if the upper redundancy operation signal UNXEB0 is disabled.
Enablement of the first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ depends on the lower redundancy operation signal DNXEB0.
For example, the first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ do not select the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0, regardless of any signal for selecting the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0, if the lower redundancy operation signal DNXEB0 is enabled. This is to prevent selection of a failed memory cell. On the other hand, the first to eleventh lower memory cell region selection units DBS00 to DBS09 and DBS09′ select one or more of the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0 according to a signal for selecting the first to tenth lower normal memory cell regions DM00 to DM09 and DM09′ of the first lower memory cell region group DMG0, if the lower redundancy operation signal DNXEB0 is disabled.
Operation of the second circuit region 150 is as follows.
If the second row address BXAR1 is input with a write command or a read command, then the second upper memory cell region control unit UFS10 to USF19 and URED1 and the second lower memory cell region control unit DFS10 to DSF19 and DRED1 determine whether to enable the upper redundancy operation signal UNXEB1 based on whether the second row address BXAR1 corresponds to a failed memory cell.
For example, the first to tenth upper comparison units UFS10 to UFS19 compare the second row address BXAR1 to each of the pre-stored comparison addresses and generate the first to tenth upper redundancy pre-signals UXHITB10 to UXHITB19. The second upper repair unit URED1 enables the upper redundancy operation signal UNXEB1 if one or more of the first to tenth upper redundancy pre-signals UXHITB00 to UXHITB09 are enabled. The first to tenth lower comparison units DFS10 to DFS19 compare the second row address BXAR1 to each of the pre-stored comparison addresses and generate the first to tenth lower redundancy pre-signals DXHITB10 to DXHITB19. The second lower repair unit DRED1 enables the lower redundancy operation signal DNXEB1 if one or more of the first to tenth lower redundancy pre-signals DXHITB10 to DXHITB19 are enabled.
Enablement of the first to tenth upper memory cell region selection units UBS10 to UBS19 depends on the upper redundancy operation signal UNXEB1.
For example, the first to tenth upper memory cell region selection units UBS10 to UBS19 do not select the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1, regardless of any signal for selecting the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1, if the upper redundancy operation signal UNXEB1 is enabled. This is to prevent selection of a failed memory cell. On the other hand, the first to tenth upper memory cell region selection units UBS10 to UBS19 select one or more of the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1 according to a signal for selecting the first to tenth upper normal memory cell regions UM10 to UM19 of the second upper memory cell region group UMG1, if the upper redundancy operation signal UNXEB1 is disabled.
Enablement of the first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ depends on the lower redundancy operation signal DNXEB1.
For example, the first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ do not select the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1 regardless of any signal for selecting the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1 if the lower redundancy operation signal DNXEB1 is enabled. This is to prevent selection of a failed memory cell. On the other hand, the first to eleventh lower memory cell region selection units DBS10 to DBS19 and DBS19′ select one or more of the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1 according to a signal for selecting the first to tenth lower normal memory cell regions DM10 to DM19 and DM19′ of the second lower memory cell region group DMG1, if the lower redundancy operation signal DNXEB1 is disabled.
The conventional semiconductor device 100 has the following problem.
The first circuit region 130 blocks a path for selection of the first memory region 120 when the first row address BXAR0, corresponding to a failed memory cell, is input. The second circuit region 150 blocks a path for selection of the second memory region 140 when the second row address BXAR1, corresponding to a failed memory cell, is input. Given this case, a time point when the second circuit region 150 blocks the path for selection of the second memory region 140 is later than the time point when the first circuit region 130 blocks the path for selection of the first memory region 120. The problem is described hereinafter with reference to FIGS. 4 and 5.
FIG. 4 is a block diagram illustrating the longest path in the first circuit region 130, from the start of transmission of the first row address BXAR0 to completion of transmission of the lower redundancy operation signal DNXEB0.
FIG. 5 is a block diagram illustrating the longest path in the second circuit region 150, from the start of transmission of the second row address BXAR1 to completion of transmission of the lower redundancy operation signal DNXEB1.
Referring to FIG. 4, the longest path in the first circuit region 130 corresponds to where the first row address BXAR0 is identical to the pre-stored comparison address stored in the first lower comparison unit DFS00 and the eleventh lower memory cell region selection unit DBS09′ is disabled according to the lower redundancy operation signal DNXEB0. In this case, the longest path in the first circuit region 130 is sum of paths for transmission of the first row address BXAR0 (2K[μm]), the first lower redundancy free signal DXHITB00 (1K[μm]) and the lower redundancy operation signal DNXEB0 (3K[μm]), which corresponds to 6K[μm].
On the other hand, referring to FIG. 5, the longest path in the second circuit region 150 corresponds to where the second row address BXAR1 is identical to the pre-stored comparison address stored in the tenth lower comparison unit DFS19 and the eleventh lower memory cell region selection unit DBS19′ is disabled according to the lower redundancy operation signal DNXEB1. In this case, the longest path in the second circuit region 150 is sum of paths for transmission of the second row address BXAR1 (4K[μm]), the tenth lower redundancy free signal DXHITB19 (1K[μm]) and the lower redundancy operation signal DNXEB1 (3K[μm]), which corresponds to 8K[μm].
As described above, the longest path in the second circuit region 150 is longer than the longest path in the first circuit region 130. This is because the first and second circuit regions 130 and 150 are disposed asymmetrically about the peripheral region 110 and thus the second circuit region 150 has a longer path than the first circuit region 130.
The discrepancy that occurs at the time point when the second circuit region 150 blocks the path for selection of the second memory region 140 is later than the time point when the first circuit region 130 blocks the path for selection of the first memory region 120 and this causes deterioration of timing parameters of the semiconductor device.